FIG. 1 shows a prior art thin film transistor 10 comprising a conductive silicon gate 12, a heavily doped p-type (p+) thin film active or source region 14, a p+ thin film active or drain region 16, and a lightly doped n-type (n-) thin film channel region 18. Thin film transistor 10 is formed over a silicon substrate 20 and an oxide isolation layer 22. Gate 12 has a top surface 24 which is covered by oxide layer 22. Isolation oxide layer 22 insulates gate 12 from thin film active regions 14 and 16 and from thin film channel region 18. Isolation oxide layer 22 is typically no more than about 700 Angstroms thick over top surface 24 of gate 12 to allow effective gating of thin film transistor 10 by top surface 24.
It is often desired to connect a conductively doped active region of a thin film transistor to a semiconductor region of a different, opposite conductivity type. The semiconductor region may be an active region of another transistor, a conductive runner in a memory circuit, or another semiconductor region to which the thin film transistor active region must be connected. This is the case in FIG. 1, where thin film transistor p+ drain region 16 is connected to an n+ semiconductor region 28.
This connection forms a parasitic diode at the junction of thin film p+ drain region 16 and n+ semiconductor region 28. The parasitic diode is detrimental to circuit operation even when it is subject only to a forward bias because of the voltage drop it causes. If the parasitic diode is subject to being reverse biased, its presence can be fatal to circuit operation. Yet, such a parasitic diode is characteristic of many circuits utilizing thin film transistors.